Ultra low power (ULP) miniature devices are enabling a new generation of applications for areas such as healthcare and wireless environmental control. Development of these applications is costly, however, as managing strict resource constraints can lead to high design complexity. For example, many require a significant amount of on-chip processing to extract information locally and thereby reduce the use of power hungry components like radios See S. Jocke, J. Bolus, S. N. Wooters, A. D. Jurik, A. C. Weaver, T. N. Blalock, and B. H. Calhoun, “A 2.6-μW Sub-threshold Mixedsignal ECG SoC,” Symposium on VLSI Circuits, 2009, the disclosure of which is hereby incorporated by reference herein in its entirety. The large variety of ULP projects and frequent changes to their requirements make flexibility a desirable attribute in this design space.
Existing approaches fail to provide both flexibility and the desired energy efficiency. Commercial processors and field programmable gate arrays (FPGAs) are far too inefficient for the ULP space, but alternatives using sub-threshold (sub-VT) operation have emerged as an energy efficient alternative. Circuits operating in sub-VT have VDD levels that are less than the threshold voltage of the transistors in the circuits, VT. Sub-VT microprocessors have shown very low energy per instruction (See S. Jocke, J. Bolus, S. N. Wooters, A. D. Junk A. C. Weaver, T. N. Blalock, and B. H. Calhoun, “A 2.6-μW Sub-threshold Mixedsignal ECG SoC,” Symposium on VLSI Circuits, 2009 and B. Zhai, L. Nazhandali, J. Olson, A. Reeves, M. Minuth, R. Helfand, S. Pant, D. Blaauw, and T. Austin, “A 2.60 pJ/Inst Subthreshold Sensor Processor for Optimal Energy Efficiency,” Symposium on VLSI Circuits, 2006, the disclosures of which are hereby incorporated by reference herein in their entirety), but their simple instruction set architecture (ISAs) require many 1000s of instructions to perform significant computing. Sub-VT ASICs give high efficiency (for example, see Y. Pu, J. P. de Gyvez, H. Corporaal, and Y. Ha, “An Ultra-Low-Energy/Frame Multi-Standard JPEG Co-Processor in 65 nm CMOS with Sub/Near-Threshold Power Supply,” ISSCC, 2009, the disclosure of which is hereby incorporated by reference herein in its entirety), but are inflexible and thus expensive to produce for low-volume projects. Today, FPGAs commercially compete mostly in the high performance space. ULP FPGAs could take advantage of a balanced tradeoff between hardware efficiency and flexibility.